Programmable logic array
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United States of America Patent
Stats
-
Jul 14, 1998
Grant Date -
N/A
app pub date -
Nov 21, 1995
filing date -
Nov 21, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one aspect, the EEPROM arrays are placed on a first chip and the PLA logic circuitry a second chip. The first and second chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips. The separate chips are fabricated concurrently to reduce turn-around time.
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