Importance

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Abstract

The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output. When an element in the second logical network responsive to a latch with a higher reference voltage fraction provides an output within a preset time, its output supersedes that of the lower individual element and prevents all lower elements in such logical network from responding. In this way, only the element in the second logical network responsive to the highest reference voltage fraction within the preset time provides an output after the latches are rendered non-transparent by a second clocking signal. Elements in the second logical network are strobed by a third clocking signal at a later preset time to indicate the input voltage magnitude.

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First Claim