Importance

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Abstract

The semiconductor memory device of the present invention is provided with at least: a first sync-signal generation circuit that generates and outputs a first sync-signal synchronized with any of a first clock inputted from the outside and a second and third clock inputted after the first clock; a first delay circuit that delays the first sync-signal by a prescribed time interval and outputs the result as a second sync-signal; a first latch circuit that latches the second sync-signal; a second latch circuit that latches the first sync-signal; and a third latch circuit that detects that both the first and second latch circuits have latched the second sync-signal and the first sync-signal, respectively, and latches this detection; the output of the third latch circuit then being used to control a pipeline circuit.

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First Claim