Programmable compensating device to optimize performance in a DRAM controller chipset
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United States of America Patent
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Jul 14, 1998
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N/A
app pub date -
May 13, 1996
filing date -
May 13, 1996
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Abstract
A programmable compensating device for optimizing performance in a DRAM controller chipset, comprising process monitors for measuring process speeds of integrated circuits in the chipset, evaluation means for comparing the measured process speeds and identifying a slowest integrated circuit, and delay modules for reducing measured process speeds as necessary to match the process speed of the slowest integrated circuit, whereby DRAM access time is minimized to permit more frequent DRAM accesses, thereby optimizing chipset performance.
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