Method of preventing cache corruption during microprocessor pipelined burst operations
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United States of America Patent
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Jul 14, 1998
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N/A
app pub date -
Dec 4, 1995
filing date -
Oct 14, 1994
priority date (Note) -
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Abstract
In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.
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