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Abstract

There is provided a fault tolerant clock system for a synchronous design using N-way combinatorial voting schemes for N greater than 3. The system comprises a plurality of clock circuits for generating clock signals and a voting circuit that is connected to each clock circuit for receiving the clock signals and generating an output signal. The voting circuit produces an output signal that is in agreement with a majority of the clock signals and maintains the output signal at a previous output level when the majority of the clock signals is not detected by the voting circuit. From another viewpoint, the voting circuit maintains the output signal at the previous current level when a minority of agreeing clock signals is not detected by the voting circuit.

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First Claim