Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline
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United States of America Patent
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Jul 21, 1998
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N/A
app pub date -
Oct 28, 1996
filing date -
Oct 28, 1996
priority date (Note) -
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Abstract
A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.
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