Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
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United States of America Patent
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-
Jul 21, 1998
Issued Date -
N/A
app pub date -
Jan 3, 1995
filing date -
Sep 7, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
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