Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips
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United States of America Patent
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Jul 28, 1998
Issued Date -
N/A
app pub date -
Aug 16, 1995
filing date -
Aug 22, 1994
priority date (Note) -
Expired
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Abstract
A fabrication method for manufacturing a monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.
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