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Abstract

A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.

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First Claim