Multi-finger MOS transistor with reduced gate resistance
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 4, 1998
Issued Date -
N/A
app pub date -
Nov 15, 1996
filing date -
Aug 27, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully