System and method for using a frame buffer in cached mode to increase bus utilization during graphics operations
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 4, 1998
Grant Date -
N/A
app pub date -
Oct 5, 1995
filing date -
Oct 5, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A system and method for increasing utilization of a system bus and frame buffer throughput in a graphic display system. The frame buffer is changed from cache inhibited mode to cached mode in order to take advantage of the burst mode of system bus in which a plurality of values are transferred to the frame buffer following one address. Data coherency is maintained between the cache and the frame buffer by invalidating a cache-line before writing to the cache-line, and by explicitly flushing the cache-line after the cache-line is filled with data.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully