System and method to reduce jitter in digital delay-locked loops
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United States of America Patent
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Aug 4, 1998
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N/A
app pub date -
Feb 29, 1996
filing date -
Feb 29, 1996
priority date (Note) -
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Abstract
The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit employing the concept of a lock-and-leave circuit. This has the effect of fine tuning the delay determined by the lock-and-leave circuit. Mode bits allow a user to control the rate at which fine tuning occurs. Three update rates are provided in a preferred embodiment of the present invention. They are slow, medium, and fast.
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