Extracting accurate and efficient timing models of latch-based designs
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United States of America Patent
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Aug 4, 1998
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N/A
app pub date -
Dec 29, 1995
filing date -
Dec 29, 1995
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Abstract
A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.
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