Importance

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Abstract

An apparatus for processing sum of the absolute differences (SAD) is disclosed. A novel circuit is disclosed which eliminates the requirement of taking the absolute value of intermediate partial sum results. The absolute value function is only needed after the final summation stage. Subtraction units take the difference between each pair of values to be processed. The output of the subtraction units are input to a first level of two input summation units. If there is more than one summation unit in the first level, the output of these summation units are input to a second level of summation units. At each level half the number of units are required until a level is reached having only one unit. The absolute value of the last unit is then taken which forms the final SAD result. Each summation unit performs an addition on its two inputs while preserving the magnitude of their sum. Depending on the sign of one of the inputs, the two inputs are either added to each other or subtracted from each other. The sign bit of both inputs are checked in order to determine whether to add or subtract. In addition, the present invention can be implemented as a sum of the absolute values (SA) generator for adding any type of values and not just for difference values. The SA generator likewise preserves the magnitude of the partial sum results thus requiring only a single absolute value function after the final summation unit.

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First Claim