Memory device having selectable redundancy for high endurance and reliability and method therefor
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United States of America Patent
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Aug 11, 1998
Grant Date -
N/A
app pub date -
Jul 10, 1997
filing date -
Jul 10, 1997
priority date (Note) -
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Abstract
A memory device having selectable redundancy for maintaining high endurance and high reliability. The memory device has two memory arrays wherein both memory arrays have a plurality of address locations for storing data. A switching unit is used to removeably connect the address locations of the first memory array means to corresponding address locations of second memory array in order to produce a first memory array having redundant address locations. If high reliability and redundancy is not required, a signal may be sent to the switching unit to disconnect the address locations of the first memory array from the corresponding address locations of the second memory array means to produce a memory device having an increased amount of address locations for storing data as compared to the first memory array having redundant address locations.
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