DC offset reduction in a transmitter
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United States of America Patent
Stats
-
Aug 11, 1998
Grant Date -
N/A
app pub date -
Oct 23, 1996
filing date -
Oct 24, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A transmitter comprising at least first and second phase related signal paths, respective frequency up-converters, a combiner for combining the output of the respective frequency up-converters and for supplying the combined signal to a power amplifier. A feedback loop is provided which has a coupler for deriving a portion of the power amplifier output signal and supplying it to first and second phase related feedback paths. Each of the feedback paths comprises frequency down-converters. The dc offset is measured at the respective inputs of the frequency up-converters when the feedback around the linearization loop is reduced to zero without altering the dc offsets produced at the outputs of the frequency down-converters. Subtractors subtract the measured dc offsets from the feedback loop error signals.
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