N-dimensional modified hypercube
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United States of America Patent
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Aug 11, 1998
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app pub date -
Jul 28, 1994
filing date -
Nov 13, 1990
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Abstract
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a 'cluster ring'. Corresponding nodes of eight cluster rings are connected into rings in the W dimension.
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