Low cost, highly parallel memory tester
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United States of America Patent
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Aug 11, 1998
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N/A
app pub date -
Sep 9, 1997
filing date -
Sep 9, 1997
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Abstract
Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.
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