Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes
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United States of America Patent
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Aug 18, 1998
Grant Date -
N/A
app pub date -
Dec 19, 1996
filing date -
Dec 19, 1996
priority date (Note) -
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Abstract
In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.
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