Importance

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Abstract

A programmable logic device in accordance with the present invention includes a partially populated switch matrix for coupling a plurality of logic blocks. Having a partial switch matrix reduces the silicon area requirement of the device. In addition, the capacitive loading is reduced, which improves propagation speed and lowers the power requirement of the sense amps, since smaller sense amps can be used. Bypass means are provided to allow the propagation bit lines (i.e. carry and shift lines) to bypass one or more logic block. Each of the logic blocks includes a plurality of logic cells. Means are provided among the logic cells to provide bypass capability for the propagation lines among the logic cells. The logic cells feature means for reverse propagation of the carry and shift bits among the logic cells. The logic cells of the present invention also feature reverse propagation with bypass.

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First Claim