DC application circuit with suppressed DC magnetization

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United States of America Patent

PATENT NO 5796279
SERIAL NO

08433453

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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To a current mirror circuit or a voltage regulator are coupled a primary winding of a transformer (T.sub.3 or T.sub.4) or a choke coil (L.sub.2 or L.sub.3). Transistors (Q.sub.1 or Q.sub.2) making up a current mirror circuit or the voltage regulator are alternatingly bypassed by a bypass circuit constituted of a capacitor (C.sub.2) and other elements. A DC magnetization which may be otherwise caused in a core or a yoke of the transformer (T.sub.3) or the choke coil (L.sub.2) is canceled by allowing direct currents to flow in opposite directions to each other through the primary winding of the transformer (T.sub.4) or through the choke coil (L.sub.2). Alternatively, the DC magnetization which may be otherwise caused in the core or the yoke of the transformer (T.sub.4) or the choke coil (L.sub.3) is significantly suppressed by restricting the direct currents flowing through the primary winding of the transformer (T.sub.4) or the choke coil (L.sub.3). This results in no necessity to provide a gap in a magnetic circuit, ensuring the reduction in size of the entire circuit configuration including the transformer (T.sub.3) as well as improved characteristics.

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Patent Owner(s)

Patent OwnerAddress
PARADYNE CORPORATION8545 126TH AVENUE N LARGO FL 33773

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ichikawa, Syuzi Tokyo, JP 3 7
Umeda, Kazuhiro Tokyo, JP 44 101

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