Method and apparatus for designing circuits for wave pipelining
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United States of America Patent
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Aug 18, 1998
Issued Date -
N/A
app pub date -
Feb 6, 1997
filing date -
Sep 16, 1994
priority date (Note) -
Expired
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Abstract
A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.
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