Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device
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United States of America Patent
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Aug 18, 1998
Grant Date -
N/A
app pub date -
May 19, 1997
filing date -
May 19, 1997
priority date (Note) -
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Abstract
A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.
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