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Abstract

A digital high-speed printing system architecture for processing contiguous raster-image data blocks for transmission to a marking engine, comprises a central processing unit ('CPU') and at least one video RAM device. Each video RAM device includes a dynamic band RAM, a serial access memory, a random access port for transmitting and receiving image data blocks to and from the dynamic band RAM, and a serial port for transmitting and receiving image data blocks to and from the serial access memory. The video RAM devices perform bi-directional image data block transfers between the dynamic band RAM and the serial access memory. Furthermore, the video RAM devices transfer image data blocks to and from the serial access port, and simultaneously transfer of image data blocks to and from the random access port. A CPU data bus is coupled between the CPU and the random access port for providing CPU access to the dynamic band RAM, such that the CPU can perform mapping operations on the image data blocks in dynamic band RAM. A dispatch FIFO is coupled to the marking engine; and serial bus is connected between the dispatch FIFO and the serial port, such that image data blocks can be dispatched from the serial access memory to the marking engines over the serial bus. Therefore, the system architecture allows for the dispatching of image data blocks from the serial access memory to be performed simultaneously to the mapping of image data blocks in dynamic band RAM.

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