Importance

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Abstract

An ATM cell switch includes a plurality of link controllers, each of which has a leaky bucket processor to monitor and control cell flow rates. Each of the leaky bucket processors includes a pair of buckets. Each processor times the arrival of each ATM cell in the respective link controller, calculates the time interval between the reception of two consecutive cells on the same connection, simultaneously determines the resultant level in both of the buckets from the calculated time interval and a stored predetermined regular bucket increment, compares the resultant level with a predetermined maximum level, and discards or changes the CLP of the current cell if the resultant level exceeds the predetermined maximum. According to a preferred embodiment of the invention, timing is effected with a 32-bit timer, but only the least significant 16-bits are used to time stamp cells. The time interval between two cells is calculated with two 16-bit adder/subtractors and two 16-bit buckets are thereby simultaneously controlled. The 32-bit routing table data is split into 16 lsb and 16 msb which are directed to respective of the adder/subtractors. A sequence of simultaneous operations in each of the adder/subtractors determine the eligibility of cells and the resultant bucket levels.

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First Claim