Method and apparatus for performing microcode paging during instruction execution in an instruction processor
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United States of America Patent
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Aug 18, 1998
Grant Date -
N/A
app pub date -
Jan 14, 1997
filing date -
Jan 14, 1997
priority date (Note) -
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Abstract
Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.
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