Importance

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Abstract

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.

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First Claim