Method and system for performance monitoring time lengths of disabled interrupts in a processing system
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United States of America Patent
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Aug 18, 1998
Grant Date -
N/A
app pub date -
Oct 2, 1995
filing date -
Oct 2, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and system for identifying inhibited interrupts in a processor system, the processor system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes initializing the at least one PMC and counting a number of cycles or occurrences with the at least one PMC that exceptions are ignored during a predetermined sampling period. In a second aspect the method and system provides for initializing at least one PMC and counting a number of cycles or occurrences with the at least one PMC that an interrupt is pending during the predetermined sampling period. The counted number of cycles/occurrences assists in identifying potential areas of improving system performance in order to reduce the counted values.
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