Method and apparatus for fault tolerant BIOS addressing
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 18, 1998
Issued Date -
N/A
app pub date -
Jul 10, 1997
filing date -
Oct 17, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully