Importance

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Abstract

In the manufacture of liquid-crystal display devices and other large-area electronics devices, electrostatic discharge damage (ESD) of tracks and other thin-film circuit elements can result during ion implantation and/or during handling. This damage is avoided by connecting the thin-film circuitry in a charge leakage path with gateable TFT links (45). These links (45) are TFTs (45) with a common gate line (7) for applying a gate bias voltage to control current flow through the links, e.g to turn off the TFTs (45) during testing of the device circuit. In accordance with the present invention the gateable links (45) in the leakage path are removed simultaneously by applying a sufficiently high gate bias (Vg2) to the common gate line (7) to break the links (45) by evaporating at least the channel regions (6) of the TFTs. A suitable thin-film structure is chosen for the TFTs (45) to facilitate evaporating their channel regions (6) in this manner. The TFTs (45) may have a very thin gate dielectric layer (8), and a channel region (6) which is narrowed in the area of overlap with the gate (7). An over-layer 44 may protect the device circuitry from debris resulting from the blowing the links (45). This protective layer (44) may have windows (42) which expose the gateable links (45).

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First Claim