Vertical type semiconductor device and gate structure

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United States of America Patent

PATENT NO 5798550
SERIAL NO

08469622

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Abstract

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The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.

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Patent Owner(s)

  • NIPPONDENSO CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kuroyanagi, Akira Okazaki, JP 44 1047
Okabe, Yoshifumi Anjo, JP 32 304
Tomatsu, Yutaka Okazaki, JP 17 203
Tsuzuki, Yasuaki Anjo, JP 6 52
Yamaoka, Masami Anjo, JP 31 486

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