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Abstract

A complex programmable logic device (CPLD) is disclosed which includes a set of logic blocks each containing a product term array and a set of macrocells. A clocking arrangement is provided which allows selection between synchronous and asynchronous clock signals for input to each macrocell. The clocking arrangement is hierarchical. More specifically, a synchronous clock multiplexer is provided, within each logic block, for reducing an input set of N synchronous clock signals, and their complements, to a reduced set of M synchronous clock signals. The selected synchronous clock signals, and J product term asynchronous clock signals, or their complements, provided by the corresponding product term array, are routed into each of the macrocells of the logic block. An additional multiplexer is provided within each macrocell for selecting one clock signal from among the M synchronous clock signals and the J product term signals. The hierarchical clocking arrangement provides considerable flexibility for selecting clocking signals, both on a block by block basis, and on a macrocell by macrocell basis yet requires relatively modest chip resources for implementation. A specific example is described herein where in N is six, M is three and J is one.

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First Claim