Integrated circuit layout
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United States of America Patent
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Sep 1, 1998
Issued Date -
N/A
app pub date -
Sep 12, 1996
filing date -
Feb 7, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The invention quickly produces a dense layout for an integrated circuit that enables a smaller die to be used to implement the integrated circuit than would otherwise be the case, resulting in a desirable size reduction in the final packaged integrated circuit. The invention combines routing space estimation and adjustment (a technique similar to channel-based global routing) with area-based detailed routing, resulting in an approach that provides the benefits of both channel-based and area-based layout techniques while minimizing the disadvantages of those techniques.
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