Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads
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United States of America Patent
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Sep 1, 1998
Grant Date -
N/A
app pub date -
Apr 22, 1996
filing date -
Apr 22, 1996
priority date (Note) -
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Abstract
A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node. The state machine launches READs to the node only when an unallocated buffer slot is available to service the corresponding READ RESPONSE.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| APPLE INC | ONE APPLE PARK WAY CUPERTINO CA 95014 |
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Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Flaig, Charles M | Cupertino, CA | 11 | 421 |
| Kelly, James D | Aptos, CA | 74 | 1222 |
| Krein, William Todd | San Jose, CA | 7 | 386 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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