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Abstract

An apparatus and method for providing a built-in self-test functional system block (BIST FSB) for self-testing a network interface integrated circuit having a Universal Test & Operations PHYInterface for ATM (UTOPIA) interface. The BIST FSB includes a random number generator, a signature analyzer, two cell counters, and a state machine for controlling the BIST FSB. Means are provided for looping the transmitter of the network interface integrated circuit back to the receiver of the network interface integrated circuit. When the BIST test is started, the state machine waits until the receiver is synchronized. Then user cells are generated and fed to the transmitter for the network interface integrated circuit. At the same time, cells on the receive side are collected and compressed into a signature. When all of the cells have been received, the signature is compared with a precalculated signature. If the signatures match, the test is passed. The BIST FSB in its self-test mode disables user data from entering the network interface integrated circuit and inserts its own data from a random number generator. The BIST monitors data going from the network interface integrated circuit receiver back to BIST. This data is 'compressed' into one number and compared with a predetermined signature in a signature analyzer.

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First Claim