Importance

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Abstract

A method and apparatus for controlling accesses to DMA control registers, specifically operating according to a Distributed Direct Memory Access (DDMA) protocol. When an access to a peripheral device ends in a Master Abort due to the failure of the peripheral device to respond to the DDMA Master component during a DDMA transaction, a System Management Interrupt (SMI#) is generated to the central processing unit. In the resulting execution of the System Management Mode code by the CPU, the cause of the peripheral component not responding (e.g., that the peripheral is in a low power mode, the connection between the DDMA master and the peripheral is interrupted, etc.) is determined. The CPU, executing SMM code, takes steps to correct the problem. For example, if the peripheral is powered down, the CPU will power it up so that the DDMA transaction can subsequently occur. Alternatively, when BIOS is used to power down a peripheral device, the DDMA Master component can determine the peripheral's power status prior to trying the DMA access. If the peripheral device is powered down, the DDMA Master component issues an SMI# to the CPU to cause the peripheral to be powered up prior to the DDMA transaction.

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First Claim