Importance

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Abstract

A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit. A RAS multiplexer has inputs for an output of the refresh RAS circuit and for data access RAS, and has an output connected to RAS output terminals of the memory controller for connection to an external dynamic random access memory to effect refresh. The microprocessor unit, which may be integrated onto a single integrated circuit chip with the refresh and memory controller, has a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes configuration registers and circuitry for controlling the access thereto, including circuitry for determining memory address type and bank sizes.

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First Claim