Process for manufacturing a packaged semiconductor having a divided leadframe stage

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5804468
SERIAL NO

08561421

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Abstract

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A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.

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Patent Owner(s)

  • FUJITSU LIMITED;KYUSHU FUJITSU ELECTRONICS LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hamano, Toshio Kawasaki, JP 32 757
Hayakawa, Michio Kawasaki, JP 19 237
Ikemoto, Yoshihiko Kawasaki, JP 15 185
Kubota, Yoshihiro Kawasaki, JP 169 1708
Miyaji, Naomi Satsuma-gun, JP 9 146
Saigo, Yukio Satsuma-gun, JP 7 191
Sakoda, Hideharu Kawasaki, JP 26 1361
Sono, Michio Kawasaki, JP 28 1063
Tsuji, Kazuto Kawasaki, JP 54 2584
Yamaguchi, Ichiro Kawasaki, JP 45 882
Yoneda, Yoshiyuki Kawasaki, JP 69 2786

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