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Abstract

A method and circuitry for testing a memory to determine its column address organization are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes a controllable multiplexer that selects certain combinations of address bits for use as column address bits to be applied to the memory; the selection of the multiplexer is controlled by the contents of a memory array type register associated with the memory or memory bank. In operation, a first data word is written to memory using a first address, and a second data word is written to memory using a second address that is spaced apart from the first address by a specified increment related to a trial number of column address bits of the memory. If the trial number of column address bits is too large, the second data word will overwrite the first as the column address portions of the first and second addresses will coincide; if the trial number of column address bits is accurate, however, the second data word will write to a different column address, leaving the first data word properly stored. The disclosed microprocessor unit, which may be integrated onto a single integrated circuit chip with the memory controller, also has a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes configuration registers and circuitry for controlling the access thereto, including circuitry for determining memory address type and bank sizes.

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First Claim