In a pipelined processor, setting a segment access indicator during execution stage using exception handling
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United States of America Patent
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Sep 8, 1998
Grant Date -
N/A
app pub date -
Feb 23, 1996
filing date -
Feb 23, 1996
priority date (Note) -
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Abstract
In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circuit for, and method of, setting a segment access indicator associated with a segment of the system memory being accessed by the processor. The circuit includes: (a) exception generating circuitry to generate an exception when the segment access indicator requires setting and (b) exception handling circuitry, invoked by the processor in response to generation of the exception, to flush the execution pipeline of instructions following a segment load instruction, set the segment access indicator and load an address pointer of the processor with an address corresponding to a specified location within the segment.
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