System for FIFO informing the availability of stages to store commands which include data and virtual address sent directly from application programs
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United States of America Patent
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Sep 8, 1998
Issued Date -
N/A
app pub date -
Mar 28, 1997
filing date -
May 15, 1995
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A digital system which uses an arrangement of one or more parallel FIFO buffers in which each FIFO buffer handles data from only one application program at any time. In order to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer, each FIFO buffer includes a flow control register which must be read by the processing unit running the application before writing data to an input/output device. The register stores a value which indicates the amount of space available in the FIFO buffer to which data may be written. Reading this register tells the application program how much data may be written without running the risk of overflowing the data storage area which the input/output device has available.
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