Shielded delay line and method of manufacture
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United States of America Patent
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-
Sep 15, 1998
Grant Date -
N/A
app pub date -
Jul 29, 1996
filing date -
Jul 29, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A thin film transmission line, delay line constructed on a ceramic substrate. A serpentine, transmission line conductor and a surrounding, coplanar border ground are plated in registry onto the substrate. Discrete ground paths which project from the border are interspersed between the conductor windings to electrically shield adjacent windings. A hard coat epoxy resin covers the signal layer, which may support a sputtered ground plane that is connected to the border ground. An alternative delay line provides overlying ground fingers within the dielectric covering layer which are aligned to the channel spaces between the conductor windings. Both assemblies provide an increased number of conductor lines per chip. Edge coupled terminations are provided at the substrate to accommodate multi-layer assemblies of the delay line and/or circuit terminations.
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