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Abstract

A non-inverting pass gate local wordline scheme for block architecture memory arrays is described which includes two switches connected in parallel which may be driven by complementary control signals. A clamping switch may be connected to the local wordline to clamp the local wordline to a power supply voltage at a low logic level whenever the pass gate blocks an input signal. When a particle or defect creates a short which short circuits a local wordline to a global wordline, the global wordline may be permanently disabled by pulling it LOW. Regardless of the states and/or polarities of the BLOCK and BLOCK signals, the local wordline is permanently held LOW because the pass gate is non-inverting. The present invention may thus reduce power in a memory device by preventing a row of memory cells from unnecessarily drawing unused and/or unusable current.

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First Claim