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Abstract

A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fraction part, with each shift of one block associated with an increment or decrement of the exponent part by one count. This format illustrated is implemented as a format suitable for the accuracy greater than the IEEE 32-bit floating-point format, and is intended to be implemented in machines having byte-wide (8 bit) data streams. The preferred format consists of a sign bit, 7 exponent bits and 4 fraction bytes of eight bits for a total of 40 bits. This format and implementation allows floating-point commands to be executed in a fixed small number of cycles, thus advancing the capabilities of doing floating-point arithmetic on a SIMD machine. The floating-point implementation is adaptable to multiprocessor parallel array processor computing systems and for parallel array processing with a simplified architecture adaptable to chip implementation. The array provided is an N dimensional array of byte-wide processing units each coupled with an adequate segment of byte-wide memory and control logic. A partitionable section of the array containing several processing units is contained on a silicon chip arranged with eight elements of the processing array each preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle. A processor system (or subsystem) comprises an array of pickets, a communication network, an 1/0 system, and a SIMD controller consisting of a microprocessor, a canned-routine processor, and a microcontroller that runs the array.

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