Block clock and initialization circuit for a complex high density PLD
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United States of America Patent
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Sep 22, 1998
Issued Date -
N/A
app pub date -
Nov 5, 1996
filing date -
Jun 2, 1995
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Abstract
A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.
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