Executing speculative parallel instructions threads with forking and inter-thread communication
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United States of America Patent
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Sep 22, 1998
Grant Date -
N/A
app pub date -
Feb 3, 1995
filing date -
Feb 3, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.
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