Importance

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Abstract

A write controller for a signal switch with a linearly searchable memory eliminates the need to maintain an ordered list of free addresses. The write controller utilizes a hardware encoded bit map and search logic to search linearly for memory locations that do not contain valid data and can therefore be written to. The search stops at the first memory location where the bit map tag indicates that the memory location is available, and then the write control logic unit associated with that memory location sends a kill signal that tells downstream write control logic units associated with other memory locations to deactivate. The write controller writes the data into the selected memory location and flips the status bit of that location to indicate that the memory location is no longer available for writing. The write controller then releases the restraining kill signal, allowing the next available memory location in line to receive data during the next clock cycle. The status bit for the memory location that was just written to continues to indicate that the memory location is not available for writing to until either the data is read out of the memory location or the system is reset. The memory location can during this time be read, but not written to. When a read of the location subsequently occurs in response to a read signal, the internal status bit is then flipped again so that the memory location will again be available to receive data.

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First Claim