Multi-buffered configurable logic block output lines in a field programmable gate array
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United States of America Patent
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Sep 29, 1998
Grant Date -
N/A
app pub date -
Oct 16, 1995
filing date -
Oct 16, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.
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