Differential delay line
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Sep 29, 1998
Grant Date -
N/A
app pub date -
Dec 27, 1996
filing date -
Dec 27, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A thin film differential delay line configured in a strip line assembly on ceramic substrates for PECL logic applications. A number of alternative layered constructions are disclosed. Each assembly provides complementary serpentine conductors constructed in symmetrical arrangements, i.e. side-by-side, over-under and mirrored. Bordering ground conductors at the signal layer and adjacent ground planes layers shield the delay line conductors. Termination pads having plated through vias facilitate electrical couplings between the layers.
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